f i g u r e 1 f u n c t i o n a l d i a g r a m d e s c r i p t i o n t h e s p 8 7 8 2 i s a m u l t i - m o d u l u s d i v i d e r w h i c h d i v i d e s b y 1 6 / 1 7 w h e n t h e r a t i o s e l e c t i n p u t i s l o w a n d b y 3 2 / 3 3 w h e n t h e r a t i o s e l e c t i n p u t i s h i g h . w h e n h i g h , t h e m o d u l u s c o n t r o l i n p u t s e l e c t s t h e l o w e r d i v i s i o n r a t i o ( 1 6 o r 3 2 ) a n d t h e h i g h e r r a t i o ( 1 7 o r 3 3 ) w h e n i t i s l o w . t h e d e v i c e u s e s r e s y n c h r o n i s a t i o n t e c h n i q u e s t o r e d u c e t h e e f f e c t s o f p r o p a g a t i o n d e l a y s i n f r e q u e n c y s y n t h e s i s . t h e s p 8 7 8 2 a ( c e r a m i c d i l p a c k a g e ) i s c h a r a c t e r i s e d o v e r t h e f u l l m i l i t a r y t e m p e r a t u r e r a n g e o f - 5 5 c t o + 1 2 5 c , t h e s p 8 7 8 2 b ( m i n i a t u r e p l a s t i c d i l p a c k a g e ) o v e r t h e i n d u s t r i a l r a n g e o f - 4 0 c t o + 8 5 c . f e a t u r e s a d v a n c e d r e s y n c h r o n i s a t i o n t e c h n i q u e s t o n e g a t e l o o p d e l a y e f f e c t s c m o s c o m p a tible output capability m u l t i - m o d u l u s d i v i s i o n a v a i l a b l e a s d e s c s m d 5 9 6 2 - 9 2 0 8 9 0 1 m p a a b s o l u t e m a x i m u m r a t i n g s s u p p l y v o l t a g e 6 v c l o c k i n p u t l e v e l 2 . 5 v p - p j u n c t i o n t e m p e r a t u r e + 1 7 5 c s t o r a g e t e m p e r a t u r e r a n g e : s p 8 7 8 2 a s p 8 7 8 2 b v r a t i o s e l e c t c c m o d u l u s c o n t r o l i n p u t c l o c k i n p u t c l o c k i n p u t o u t p u t v e e 1 2 2 3 4 5 7 1 6 / 1 7 3 2 / 3 3 s p 8 7 8 2 a & b march 2006 1 g h z 1 6 / 1 7 , 3 2 / 3 3 m u l t i - m o d u l u s d i v i d e r - 5 5 c t o + 1 2 5 c - 5 5 c t o + 1 5 0 c 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copy right 1999-2006, zarlink semiconductor inc. all rights reserved. ordering information sp8782/b/mp 8 pin sop/soic tubes sp8782/a/dg 8 pin cerdip tubes sp8782/b/mptc 8 pin sop/soic tape & reel sp8782/b/mp2q 8 pin sop/soic** tape & reel **pb free tin/silver/copper
2 SP8782A & b electrical characteristics unless otherwise stated, the electrical characteristics are guaranteed over the specified supply, frequency and temperature range. supply voltage , v cc = +4v to +5.5v, v ee = 0v temperature t amb = -55 c to +125 c , (SP8782A), -40 c to +85 c (sp8782b) characteristic pin value conditions min max units maximum frequency 2, 3 1 ghz input = 200-1200mvp-p (sinewave input) minimum frequency 2, 3 50 mhz input = 400-1200mvp-p min slew rate for low frequency operation 2, 3 100 v/ m s power supply current, i cc 8 60 ma output unloaded, v cc =5.5v output low voltage 7 0 1.7 v output high voltage 7 v cc -1.4 v cc v modulus control input high voltage 5 0.7v cc v cc v at driver end of 3k w resistor modulus control input low voltage 5 0 0.3v cc v at driver end of 3k w resistor modulus control input high current 5 0.6 1.2 ma via 3k w resistor to v cc modulus control input low current 5 -0.6 -1.2 ma via 3k w resistor to v cc ratio select input high voltage 1 0.6v cc v cc v ratio selected input low voltage 1 0 0.4v cc v ratio select input current 1 -10 10 m a clock to output propagation delay 2,3,7 3 ns set-up time, t s 5,7 3 ns see note 1 and fig. 3a release time,t r 5,7 3 ns see note 2 and fig. 3b notes: 1. the set-up time t s is defined as the minimum time that can elapse between l ? h transition of the modulus control input and the next l ? h output transition to ensure that the ? 16 (32) mode is obtained. 2. the release time t r is defined as the minimum time that can elapse between h ? l transition of the modulus control input and the next l ? h output transition to ensure that the ? 17 (33) mode is obtained. figure 2 typical pin connections dg 8 ratio select clock input clock input v ee v cc output nc modulus control 1 2 3 4 8 7 6 5 mp 8 v cc output nc modulus control 1 2 3 4 8 7 6 5 ratio select clock input clock input v ee
3 SP8782A & b don? care 8 (16) t r t r 8 (16) 9 (17) clock input modulus control input output don? care 8 (16) divide-by-17 (33) mode established extra pulse fig. 3a setting divide-by-16 (32) mode don? care 9 (17) t s t s 8 (16) 8 (16) clock input modulus control input output don? care 8 (16) divide-by-16 (32) mode established figure 3 timing diagrams table 1 truth table for control inputs modulus control ratio select input input 01 0 ? 17 ? 33 1 ? 16 ? 32 figure 3b setting divide - by - 17 (33 mode) figure 3a setting divide - by - 16 (32 mode)
4 SP8782A & b 1600 1400 1200 1000 800 600 400 200 0 0 200 4 00 600 8 00 1000 input frequency (mhz) input amplitude (mv p-p) * tested as spec i in table of e characteristi guaranteed * operating window figure 4 typical input characteristics 7 6 2 3 output v ee clock input divide by 16/17 or 32/33 v cc 4 8 5 modulus control input 1 ratio select 10n 3k notes 1. pin 6 is grounded to improve isolation between the output and the modulus control input. 2. the 3k w resistor on pin 5 reduces the amplitude of the modulus control signal to minimise radiation. 1n 1n figure 5 typical application showing interfacing divide by 16/17 or 32/33 * tested as specified in table of electrical characteristics notes 1. pin 6 is grounded to improve isolation between the output and the modulus control input 2. the 3k w resistor on pin 5 reduces the amplitude of the modulus control signal to minimise radiation
5 SP8782A & b j 2 j 1 j 0.5 j 0.2 0 2 j 0.2 2 j 0.5 2 j 1 2 j 2 1 0.5 0.2 j 5 2 j 5 2 5 1000 200 400 600 800 1100 figure 6 typical input impedance. test conditions: supply voltage =5v, ambient temperature =25 c, frequencies in mhz, impedances normalised to 50 w
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